?2010 fai rchild semiconductor corporation HUFA76645S3ST_f085 rev. a 75a, 100v, 0.015 oh m, n-channel, logic level ultrafet? power mosfet packaging symbol features ? ult ra low on-resistance -r ds (o n) = 0 .014 ?, v gs = 10 v -r ds ( on) = 0 . 015 ?, v gs = 5v s imulation models - temperature compensated pspice? and saber? electrical models - spice and saber thermal impedance models - www.fairchildsemi.com peak current vs pulse width curve uis rating curve switching time vs r gs cu rv es or dering inf ormation ab solu te maximum ratings t c = 25 o c, unles s otherwis e specified this product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. for a c opy of the requirements, see aec q101 at: h ttp://w ww.aecouncil.com/ reliability data can be found at: http ://www.f airchildsemi.com/product s/di screte/relia bility/index.html. all fairchild semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certif ication. jedec to-263ab ga t e source drai n (f lange) d g s p brand not e : when ordering, use the entire part number. add the suffix t to obtain the variant in tape and reel, e.g., HUFA76645S3ST. huf a76645 s3st_f085 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 100 v drain t o g ate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dg r 100 v ga t e to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 16 v drain current co nt inuous (t c = 25 o c, v gs = 5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d co ntin uous (t c = 25 o c, v gs = 10v) (f igure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d co ntin uous (t c = 100 o c, v gs = 5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d co ntin uous (t c = 100 o c, v gs = 4. 5v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d p ul sed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 75 75 63 62 f igure 4 a a a a pul s ed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . uis figu res 6, 17, 18 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d de rat e above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 2.07 w w/ o c o perat ing and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg - 55 to 175 o c max imum t emperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l p ac kage body for 10s, see techbrief tb334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c no tes : 1. t j = 25 o c t o 150 o c. ca ution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress only ratin g and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. d ata sh eet september 2010 hufa766 45s3st_f085 o-263ab 76645s huf a76645s3st_f085 t art number package qualified to aec q101 rohs compliant
ele ctrical specifications t c = 2 5 o c, u nless otherwise specified parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 12) 100 - - v i d = 250 a, v gs = 0v , t c = -40 o c (figure 12) 90 - - v zero gate voltage drain current i dss v ds = 95v, v gs = 0v - - 1 a v ds = 90v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gs s v gs = 16v - - 100 na on state specifications gate to source threshold voltage v gs (th) v gs = v ds , i d = 250 a (figure 11) 1 - 3 v drain to source on resistance r ds( on) i d = 75a, v gs = 10v (figures 9, 10) - 0.012 0.014 ? i d = 63a, v gs = 5v (figure 9) - 0.013 0.015 ? i d = 62a, v gs = 4.5v (figure 9) - 0.0135 0.0155 ? thermal specifications thermal resistance junction to case r jc t o-220 and to-263 - - 0.48 o c/w t hermal resistance junction to ambient r ja -- 62 o c/w s witching specifications (v gs = 4.5v) turn-on time t on v dd = 50v, i d = 62a v gs = 4. 5v, r gs = 2.4 ? (figures 15, 21, 22) - - 490 ns turn-on delay time t d( on) -1 7-ns rise time t r - 310 - ns turn-off delay time t d( off) -4 6-ns fall time t f - 155 - ns turn-off time t off - - 300 ns switching specifications (v gs = 10v) turn-on time t on v dd = 50v, i d = 75a v gs = 10v, r gs = 2.4 ? (figures 16, 21, 22) - - 175 ns turn-on delay time t d( on) -1 1-ns rise time t r - 106 - ns turn-off delay time t d( off) -6 9-ns fall time t f - 175 - ns turn-off time t off - - 365 ns gate charge specifications total gate charge q g( tot) v gs = 0v to 10v v dd = 50v, i d = 63a, i g( ref) = 1.0ma (figures 14, 19, 20) - 127 153 nc gate charge at 5v q g( 5) v gs = 0v to 5v - 70 84 nc threshold gate charge q g( th) v gs = 0v to 1v - 3.8 4.6 nc gate to source gate charge q gs -1 0-nc gate to drain ?miller? charge q gd -3 4-nc capacitance specifications input capacitance c is s v ds = 25v, v gs = 0v, f = 1mhz (figure 13) - 4400 - pf output capacitance c os s - 900 - pf reverse transfer capacitance c rs s - 280 - pf s ource to drain diode specifications p arameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 63a - - 1.25 v i sd = 30a - - 1.0 v reverse recovery time t rr i sd = 63a, di sd / dt = 100a/ s - - 128 ns reverse recovered charge q rr i sd = 63a, di sd / dt = 100a/ s - - 520 nc HUFA76645S3ST_f085 ?2010 fai rchild semiconductor corporation HUFA76645S3ST_f085 rev. a
t ypical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum cont inuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capab ility t c , case temperature ( o c) p ower dissipation multiplier 0 0 25 50 75 100 17 5 0. 2 0.4 0.6 0.8 1.0 1.2 125 15 0 20 40 60 80 25 50 75 100 125 150 17 5 0 i d , drain current (a) t c , case temperature ( o c) v gs = 10v v gs = 4.5v 0. 1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.0 1 2 t, rectangular pulse duration (s) z jc , normalized si ngle pulse no tes: duty factor: d = t 1 /t 2 pea k t j = p dm x z jc x r jc + t c p dm t 1 t 2 dut y cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 t hermal impedance 10 0 1000 50 2000 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -5 i dm , peak current (a) t , pulse width (s) t ransconductance may limit current in this region t c = 2 5 o c i = i 25 175 - t c 150 f or temperatures above 25 o c der ate peak cur rent as follows: v gs = 1 0v v gs = 5 v ?2010 fai rchild semiconductor corporation HUFA76645S3ST_f085 rev. a h ufa76645s3st_f085
f igure 5. forward bias safe operating area note: refer to fairchild application notes an9321 and an 9322. figure 6. unclamped inductive switching capability figure 7. transfer characteristics fig ure 8. saturation characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature t ypical performance curves ( continued) 10 10 0 1 10 100 30 0 1 50 0 10 0 s 10m s 1m s v ds , drain to source voltage (v) i d , drain current (a) li mited by r ds( on) area m ay be operation in this t j = m ax rated t c = 2 5 o c si ngle pulse 10 0 0.001 0.01 0.1 1 1 0 1 50 0 i as , a valanche current (a) t av , t ime in avalanche (ms) t av = (l)(i as )/ (1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as * r)/(1.3*rated bv dss - v dd ) + 1] st arting t j = 2 5 o c st arting t j = 1 50 o c 25 50 75 100 125 150 1.5 2.0 2.5 3.0 3.5 4. 0 0 i d, drain current (a) v gs , gate to source voltage (v) p ulse duration = 80 s duty cycle = 0.5% max v dd = 1 5v t j = 1 75 o c t j = 2 5 o c t j = - 55 o c 25 50 75 100 125 150 01 23 4 0 i d , drai n current (a) v ds , drain t o source voltage (v) v gs = 3 v v gs = 3 .5v v gs = 5 v v gs = 1 0v pul se duration = 80 s duty cycle = 0.5% max t c = 2 5 o c v gs = 4 v 15 20 25 246 81 0 10 i d = 2 0a v gs , gate to source voltage (v) i d = 7 5a r ds( on) , drain to source on resistance (m ? ) i d = 50a pul se duration = 80 s duty cycle = 0.5% max t c = 2 5 o c 1.0 1.5 2.0 2.5 3.0 - 80 -40 0 40 80 120 160 20 0 0.5 norm alized drain to source t j , junction temperature ( o c) o n resistance v gs = 10v, i d = 7 5a pul se duration = 80 s duty cycle = 0.5% max ?2010 fai rchild semiconductor corporation HUFA76645S3ST_f085 rev. a h ufa76645s3st_f085
figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an 7260. figure 14. gate charge waveforms for constant gate current figure 15. switching time vs gate resistance fi gure 16. switching time vs gate resistance t ypical performance curves ( continued) 0. 6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 200 0.4 norm alized gate t j , j unction temperature ( o c) v gs = v ds , i d = 2 50 a t hreshold voltage 1.0 1.1 1.2 -80 -40 0 40 80 120 160 200 0.9 t j , j unction temperature ( o c) norm alized drain to source breakdown voltage i d = 250 a 10 0 1000 10000 0.1 1 10 10 0 70 c, cap acitance (pf) v ds , drain to source voltage (v) v gs = 0 v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 2 4 6 8 10 0 30 60 90 120 15 0 0 v gs , gate to source voltage (v) v dd = 50v q g , gate charge (nc) i d = 75a i d = 50a waveforms in descending order: i d = 20a 200 400 600 800 1 000 1200 0 1020304050 0 swit ching time (ns) r gs , gate to source resistance ( ? ) v gs = 4.5v, v dd = 5 0v, i d = 62a t r t f t d( on) t d( off) 20 0 400 600 800 1000 1200 0 1020304050 0 swit ching time (ns) r gs , gate to source resistance ( ? ) v gs = 1 0v, v dd = 5 0v, i d = 7 5a t d( off) t r t d( on) t f ?2010 fai rchild semiconductor corporation HUFA76645S3ST_f085 rev. a h ufa76645s3st_f085
t est circuits and waveforms fi gure 17. unclamped energy test circuit figure 18. unclamped energy waveforms figure 19. gate charge test circuit figure 20. gate charge waveforms figure 21. switching time test circuit figure 22. switching time waveform t p v gs 0. 01 ? l i as + - v ds v dd r g dut va ry t p t o obtain required peak i as 0v v dd v ds bv ds s t p i as t av 0 r l v gs + - v ds v dd dut i g( ref) v dd q g( th) v gs = 1 v q g( 5) v gs = 5 v q g( tot) v gs = 1 0 v v ds v gs i g( ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d( on) t r 90% 10 % v ds 90 % 10% t f t d( off) t of f 90 % 50% 50% 10% pulse width v gs 0 0 ?2010 fai rchild semiconductor corporation HUFA76645S3ST_f085 rev. a h ufa76645s3st_f085
p spice electrical model . subckt hufa76645 2 1 3 ; rev 7 june 1999 ca 12 8 7.4e-9 cb 15 14 7.4e-9 cin 6 8 4.13e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 121 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 5.1e-9 lsource 3 7 4.4e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 8.3e-3 rgate 9 20 0.96 rldrain 2 5 10 rlgate 1 9 51 rlsource 3 7 44 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rso urcemod 2.5e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51) /abs(v (5,5 1)))*(pwr(v (5,5 1)/(1e -6*200),3.2))} .model dbodymod d (is = 3.6e-12 rs = 2.24e-3 trs1 = 2e-3 trs2 = 1.03e-6 cjo = 4.5e-9 tt = 5.1e-8 m = 0.60) .model dbreakmod d (rs = 2.5e- 1trs1 = 1e- 4trs2 = 1e-7) .model dplcapmod d (cjo = 5.4e- 9is = 1e-3 0vj = 1.0 m = 0.9) .model mmedmod nmos (vto = 1.77 kp = 7 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 0.96) .model mstromod nmos (vto = 2.11 kp = 200 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.5 kp = 0.12 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 9.6 rs = 0.1) .model rbreakmod res (tc1 = 1.05e- 3tc2 = -5e-7) .model rdrainmod res (tc1 = 8.8e-3 tc2 = 1.7e-5) .model rslcmod res (tc1 = 4e-3 tc2 = 1.5e-5) .model rsourcemod res (tc1 = 1e-3 tc2 = 2e-6) .model rvthresmod res (tc1 = -1.9e-3 tc2 = -8e-6) .model rvtempmod res (tc1 = -1.7e- 3tc2 = 1e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -4.5 voff= -2.0) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.0 voff= -4.5) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -1.0 voff= 0.5) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.5 voff= -1.0) .ends n ote: for further discussion of the pspice m odel, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1 991, written by william j. hepp and c. frank w heatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rv temp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mw eak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rsl c2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 ?2010 fai rchild semiconductor corporation HUFA76645S3ST_f085 rev. a h ufa76645s3st_f085
s aber electrical model re v 7 june 1999 template hufa76645 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 3.6e-12, cjo = 4.5e-9, tt = 5.1e-8, m = 0.60) d..model dbreakmod = () d..model dplcapmod = (cjo = 5.4e-9, is = 1e-30, vj=1.0, m = 0.9 ) m..model mmedmod = (type=_n, vto = 1.77, kp = 7, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.11, kp = 200, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.5, kp = 0.12, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.5, voff = -2.0) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -4.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0) c.ca n12 n8 = 7.4e-9 c.cb n15 n14 = 7.4e-9 c.cin n6 n8 = 4.13e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.1e-9 l.lsource n3 n7 = 4.4e-9 m.mmed n16 n6 n8 n8 = model=mmed mod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mst rongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5e-7 res.rdbody n71 n5 = 2.24e-3, tc1 = 2e-3, tc2 = 1.03e-6 res.rdbreak n72 n5 = 2.5e-1, tc1 = 1e-4, tc2 = 1e-7 res.rdrain n50 n16 = 8.3e-3, tc1 = 8.8e-3, tc2 = 1.7e-5 res.rgate n9 n20 = 0.96 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 51 res.rlsource n3 n7 = 44 res.rslc1 n5 n51 = 1e-6, tc1 = 4e-3, tc2 = 1.5e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.5e-3, tc1 = 1e-3, tc2 = 2e-6 res.rvtemp n18 n19 = 1, tc1 = -1.7e-3, tc2 = 1e-7 res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -8e-6 spe.ebreak n11 n7 n17 n18 = 121 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s 1amod sw_vcsp.s1b n 13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n 13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/200))** 3.2)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rv temp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mw eak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rsl c2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbod y rdbreak 72 71 ?2010 fai rchild semiconductor corporation HUFA76645S3ST_f085 rev. a h ufa76645s3st_f085
s pice thermal model rev 7 june 1999 hufa76645t ctherm1 th 6 6.4e-3 ctherm2 6 5 3.0e-2 ctherm3 5 4 1.4e-2 ctherm4 4 3 1.6e-2 ctherm5 3 2 5.5e-2 ctherm6 2 tl 1.5 rtherm1 th 6 3.4e-3 rtherm2 6 5 8.6e-3 rtherm3 5 4 2.3e-2 rtherm4 4 3 1.3e-1 rtherm5 3 2 1.8e-1 rtherm6 2 tl 3.9e-2 s aber thermal model sa ber thermal model hufa76645t template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.4e-3 ctherm.ctherm2 6 5 = 3.0e-2 ctherm.ctherm3 5 4 = 1.4e-2 ctherm.ctherm4 4 3 = 1.6e-2 ctherm.ctherm5 3 2 = 5.5e-2 ctherm.ctherm6 2 tl = 1.5 rtherm.rtherm1 th 6 = 3.4e-3 rtherm.rtherm2 6 5 = 8.6e-3 rtherm.rtherm3 5 4 = 2.3e-2 rtherm.rtherm4 4 3 = 1.3e-1 rtherm.rtherm5 3 2 = 1.8e-1 rtherm.rtherm6 2 tl = 3.9e-2 } r therm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th j unction cas e ?2010 fai rchild semiconductor corporation HUFA76645S3ST_f085 rev. a h ufa76645s3st_f085
? fairchild semiconductor corporation www.fairchildsemi.com trademarks the following includes registered and unregistered trademarks and se rvice marks, owned by fairchild semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. accupower ? auto-spm ? build it now ? coreplus ? corepower ? crossvolt ? ctl ? current transfer logic ? deuxpeed ? dual cool? ecospark ? efficientmax ? esbc ? ? fairchild ? fairchild semiconductor ? fact quiet series ? fact ? fast ? fastvcore ? fetbench ? flashwriter ? * fps ? f-pfs ? frfet ? global power resource sm green fps ? green fps ? e-series ? g max ? gto ? intellimax ? isoplanar ? megabuck ? microcoupler ? microfet ? micropak ? micropak2 ? millerdrive ? motionmax ? motion-spm ? optohit? optologic ? optoplanar ? ? pdp spm? power-spm ? powertrench ? powerxs? programmable active droop ? qfet ? qs ? quiet series ? rapidconfigure ? ? saving our world, 1mw/w/kw at a time? signalwise ? smartmax ? smart start ? spm ? stealth ? superfet ? supersot ? -3 supersot ? -6 supersot ? -8 supremos ? syncfet ? sync-lock? ? * the power franchise ? tinyboost ? tinybuck ? tinycalc ? tinylogic ? tinyopto ? tinypower ? tinypwm ? tinywire ? trifault detect ? truecurrent ? * serdes ? uhc ? ultra frfet ? unifet ? vcx ? visualmax ? xs? * trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical co mponents in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provi ded in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. anti-counterfeiting policy fairchild semiconductor corporation's anti-counterfeiting policy. fairchild's anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support. counterfeiting of semiconductor parts is a growing problem in t he industry. all manufacturers of semiconductor products are exp eriencing counterfeiting of their parts. customers who inadvertently purchase counter feit parts experience many problems such as loss of brand reputation, substandard p erformance, failed applications, and increased cost of production and manufacturing delays. fairchild is taking strong measures to protect ourselves and our cus tomers from the proliferation of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts eit her directly from fairchild or from a uthorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or from authorized fairchi ld distributors are genuine parts, have full traceability, meet fairch ild's quality standards for handling and storage and pr ovide access to fair child's full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and will appropr iately address any warranty issues t hat may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from u nauthorized sources. fairchild is committed to combat this glo bal problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. product status definitions definition of terms datasheet identification product status definition advance information formative / in design datasheet contains the design s pecifications for product developmen t. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specific ations. fairchild semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specificati ons on a product that is disconti nued by fairchild semiconductor. the datasheet is for reference information only. rev. i48
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